MicraGEM-Si™ – SOI MEMS Process
Micralyne’s new MicraGEM-Si™ process platform enables designers to prototype devices within defined design rules, greatly reducing the initial cost and risk of development, and speeding the time to market for MEMS-based devices.
We offer this unique silicon MEMS process to our clients through two different pathways:
a) for researchers and prototype designers, we work in collaboration with CMC Microsystems to allow designers to purchase a portion of a MEMS fabrication run through use of a multi-product wafer strategy. CMC Microsystems engages with the client, provides design documentation, and design consolidation services for MicraGEM-Si™.
b) for companies with larger volume requirements, Micralyne will provide this platform directly to company clients who require a full fabrication run or who require customization of the technology.
The platform consists of an SOI (silicon-on-insulator) base wafer with customer-defined cavities, support posts, and electrical wiring. A top SOI wafer, with optional cavities, is then fusion-bonded to the base wafer. The handle wafer is removed, leaving a precise thickness MEMS device layer. A patterned metal layer is added for high reflectivity, circuit routing, and wire bonding. The top side of the wafer can be patterned and etched to release the MEMS devices.
Micralyne’s unique process capability provides high-yield wafer bonding after several masks of pattern and etch. Alignment tolerance between the bottom layers and the final top silicon layer is within +/- 0.4 microns. This allows for complex structures such as staggered vertical comb-drive actuators, providing low voltage operation and a linear voltage vs. tilt response for micro-mirrors.
MicraGEM-Si White Paper Download:
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Purchasing a Sample Portion at:the CMC website
Please contact us for more information about MicraGEM-Si™.