Through-Silicon-Via (TSV) allows electrical connections to be formed through a silicon wafer or multi-wafer devices. Electrical connections through a silicon wafer reduce die footprints and allow interlayer connectivity. When combined with Wafer Level Packaging (WLP), TSVs minimize die size, allow conventional or flip-chip bonding, and help minimize assembly cost of the final device.

Micralyne offers polysilicon TSV technology for custom prototyping and manufacturing. Connections between layers are created through etching via holes, selective insulation, and fill-in with conductive polysilicon. This platform includes deep etched silicon trenches, isolation or grounding vias, polysilicon filling, and the option for integration in SOI wafer stacks. Customers provide TSV requirements including aspect ratio, thickness, pitch, resistivity, capacitance, geometry, and isolation resistance.

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