Wafer Level Packaging (WLP)
MicraSilQ™ (pronounced Micra-silk) wafer level packaging (WLP) technology for MEMS devices provides an all-in-one customer solution integrating wafer level fabrication, hermetic packaging and through silicon via (TSV) architecture. MicraSilQ™ MEMS reduces overall component cost, footprint, thickness and weight, while simultaneously providing improved electrical performance, reliability, and extensibility into 3D IC designs.
MicraSilQ™ can be used for a variety of microdevices. Features include:
- Insulated Through Silicon Vias (TSV) Deep Etched and Polysilicon-filled
- Electrical contacts between the MEMS
- Die and macroscale device
- Wafer level bonding processes optimized for getter films and wafer level testing
MicraSilQ™ has proven to be a cost-effective solution for applications requiring high sensitivity mechanical sensing, for RF devices operating across wide frequency ranges, and for components requiring high vacuum encapsulation. WLP products are efficiently tested to ensure 100% of critical parameters meet Micralyne’s high quality standards.
Download our Whitepaper: Advanced WLP Platform for High-Performance MEMS to learn more.
Contact us to find out more about our Wafer Level Packaging technology.